Reduction in the acquisition duration of a phase-locked loop able to reconstitute a synchronisation signal transmitted over an ip network

ABSTRACT

The present invention relates to the domain of video equipment. More specifically, it concerns a reception device that comprises the means for:
         receiving packets containing samples, that come from data sampled every T ech  period, where T ech  is from a time base synchronised on all the stations of said network,   regenerating a counting ramp having a count increment and a range value PCR_Modulus, using a phase-locked loop PLL 1  that receives the samples and that delivers local samples every T ech  period and a reconstituted clock,   initialising, at every zero-crossing of the counting ramp, an image counter that is determined by the reconstituted clock.       

     According to the invention, it comprises, further, means for determining the values of count increments.

SCOPE OF THE INVENTION

The present invention relates to the domain of video equipment.

The present invention relates more particularly to a device for thereception of a synchronisation signal on a packet switching network, forexample of the IP type, whether the network is wired (for exampleEthernet (IEEE802.3)) or wireless (for example IEEE 802.16 D-2004).

PRIOR ART

Progress in the ability of IP networks to transport all types of signal(data or video) has made it possible to use these networks as the“backbone” architecture for video studios. Of capital importance to thisevolution is therefore having a single infrastructure for the transportof data. Whereas in the past, several media were necessary to transportdifferent signal types, the multiplexing properties offered by the IPlayer enable a reduction in the number of media necessary: an IP networkthat links the different equipment.

In the prior art, the synchronisation of items of video equipment(cameras, etc.) in a studio is carried out by the transmission of asynchronisation signal commonly called “Genlock” or “Black burst”. Forexample, the Genlock signal comprises two synchronisation signals, oneis repeated every 40 ms and indicates the start of the video frame, theother is repeated every 64 μs (for a standard format and less for an HDformat) and indicates the start of lines in the video frame. Thewaveform of the synchronisation signals depends on the format of theimage transmitted over the network. For example, for a high definitionimage, the signal synchronisation has a tri-level form (−300 mV, 0V,+300 mV).

When a synchronisation signal is routed to different equipment to besynchronised by a dedicated coaxial cable, a constant transmission time,without jitter is ensured. From such a signal, all items of equipmentare able to reconstruct a timing clock that is specific to itsfunctioning, which guarantees that its functioning is rigorously inphase with all the equipment connected to the same network. For example,two cameras synchronised by a Genlock signal circulating on a dedicatedcoaxial cable each generate a video with different contents butrigorously in frequency and in phase with one another.

A known disadvantage presented by an IP/Ethernet network is that itintroduces a strong jitter in a transmission of signals, andparticularly for the transmission of a synchronisation signal. When sucha signal is routed by an IP/Ethernet connection to different items ofequipment for synchronising, this jitter results in fluctuations in thelength of time required for the information carried by thesynchronisation signal to reach the equipment.

In the prior art, devices are known for reconstructing, for each camera,a timing clock specific to this camera enabling the jitter to beovercome. The underlying principle of these devices is a highattenuation of the synchronisation signal jitter amplitude at the levelof reception. In such a way, it can be guaranteed that an imagegenerated by a camera is rigorously in phase with all of the imagesgenerated by neighbouring cameras connected to the same network.

Examples of such devices are described in the international PCTapplication FR2007/050918, they act on program clock reference (PCR)signals that represent very accurate reference clock signals. Thesedigital signals are sent to cameras across a network so that they canlocally reconstruct clock signals that are in phase with the referenceclock.

According to the prior art, the reception device comprises:

-   -   means for receiving packets containing samples of the network        coming from data sampled every T_(ee), period,    -   means for regenerating a counting ramp CSR_PCR₁ using a        phase-locked loop PLL₁,    -   means for initialising a second CPT counter every zero-crossing        of said first counter CSR_PCR₁,    -   means for generating image cues at every zero-crossing of the        said second CPT counter, and    -   means for reconstituting a synchronisation signal from said        image cues.

The phase-locked loop PLL₁ of the reception device acts as a low-passfilter that partially attenuates the jitter present in the samplesreceived PC_(r) that have circulated on the network.

Usually, two phases are distinguished in the functioning of the loopPLL₁:

-   -   a first phase, known as the “acquisition phase”, during which        the phase-locked loop PLL₁ internally produces local samples        PCR_loc₁ that are very different from the received samples        PCR_(r). This first phase begins with a reception of samples        PCR_(r) and ends when the local samples PCR_loc₁ produced by the        loop PLL₁ are very close to the samples received PCP_(R)PCR_(R).        During this functioning phase, a synchronisation signal        reconstructed on the reception side by means of the loop PLL₁ is        not in phase with the synchronisation signal on the transmission        side,    -   a second phase, known as the “continuation phase” begins at the        end of the acquisition phase and ends when a difference of        reduced amplitude between the local samples PCR_loc₁ and the        received samples PCR_(r) is detected. During this second        functioning phase, a reconstructed synchronisation signal on the        reception side is in phase with the synchronisation signal on        the transmission side.

In order to quickly obtain a synchronisation of the items of equipmentthat are connected to a network, it therefore appears to be useful toreduce a duration of the acquisition phase.

One of the purposes of the present invention is therefore to acceleratethe generation of local samples PCR_loc₁ in phase with the samplesreceived PCR_(R). To do this, the invention proposes, in comparison withthe reception devices of the prior art, to modify the generation of thecounting ramp CSR_PCR₁ to generate counting ramps CSR_PCR₁, theincrement of which, or the incrementing step ΔC, is adapted so that thedifference between the local samples and the received samples is reducedas rapidly as possible. Specifically, according to the invention, theincrementing step does not necessarily have a unit value and is signed.

SUMMARY OF THE INVENTION

For this purpose, the present invention concerns a device able toreceive packets in a packet switching network comprising at least twostations. The device comprises:

-   -   means for receiving packets containing samples PCR_(r), said        samples PCR_(r) coming from data sampled every T_(ech) period,        where T_(ech) is from a time base synchronised on all the        stations of said network,    -   means for regenerating a counting ramp CSR_PCR₁ having a count        increment value ΔC and a range value PCR_Modulus, using a        phase-locked loop PLL₁ receiving the samples PCR_(r) and further        delivering local samples PCR_loc₁ every T_(ech) period and a        reconstituted clock CLK_out₁ with a frequency value F_(out),    -   means for initialising, at every zero-crossing of the counting        ramp CSR_PCR₁, an image counter CPT that is determined by the        reconstituted clock CLK_out₁;    -   means for generating image cues at every zero-crossing of said        counter CPT; and    -   means for reconstituting a synchronisation signal from said        image cues.

According to the invention, it comprises, furthermore, means MES₁ fordetermining the count increments values ΔC.

An advantage of the invention lies in its faculty to shortenconsiderably the duration of the acquisition phase and, as a result, toreduce the duration beyond which a piece of equipment comprising areception device according to the invention is synchronised with atransmission device emitting samples on the network. The counting rampCSR_PCR₁ is generated with a count increment ΔC that is determined froma direct or indirect measure of a difference ERR between local samplesPCR_loc₁ and received samples PCR_(r).

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better understood from the following descriptionof an embodiment of the invention provided as an example by referring tothe annexed figures, wherein:

FIG. 1 shows the transmission of genlock information between two cameraslinked via an IP/Ethernet network,

FIG. 2 shows the interfacing between the analogue domain and theIP/Ethernet network,

FIG. 3 shows the regeneration of the Genlock signal on the receptionside according to the prior art,

FIG. 4 diagrammatically shows a phase-locked loop architecture of areception device according to the prior art,

FIG. 5 diagrammatically shows a phase-locked loop architecture of areception device according to the invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS OF THE INVENTION

The current analogue domain is interfaced with the IP/Ethernet networkon the transmission side, and the IP/Ethernet network is interfaced withthe analogue domain on the reception side, as illustrated in FIG. 1.

In the same figure, the transmission side comprises a “Genlock master”MGE that is connected to an IP/Analogue interface IAIP. The Genlockmaster MGE sends a Genlock signal SG0 to the interfaces IAIP.

The reception side comprises two cameras (CAM1, CAM2) each connected toan IP/Analogue interface I_IPA. The interfaces I_IPA that willeventually be included in the cameras themselves are responsible forreconstructing the Genlock signals SG1, SG2 intended for cameras CAM1,CAM2. The cameras CAM1, CAM2 each produce a video signal SV1, SV2 thatis required to be synchronised perfectly.

The transmission and reception sides are linked together by a packetswitching network that is the source of a jitter occurring in theGenlock signal SG0.

A sampling pulse, in the T_(ech), period, is generated from a firstsynchronisation layer, for example IEEE1588, and is sent to thetransmission and reception sides. Indeed, the PTP protocol (PrecisionTime Protocol) based on IEEE1588 enables synchronisation to be obtainedbetween the equipment connected on the Ethernet network to an order ofmicroseconds. In other words, all the time bases of every item ofequipment progress at the same time with a precision close to the orderof microseconds. Each of these time bases can be used in this case togenerate its own sampling pulse in the T_(ech), period. Use of theIEEE1588 layer is not a required route. Any system capable of providingsampling pulses to the various items of equipment on the network in theT_(ech) period could be suitable. For example, a 5 ms sampling pulsefrom a wireless transmission physical layer can be used.

FIG. 2 details the processing of the Genlock signal SG0 from MGE withinthe interface I_AIP.

First, a module EXS extracts the synchronisation information from thesignal SG0 in order to recover a video timing clock (noted as Clk onFIG. 2). More specifically, the module EXS is responsible for thegeneration of an image cue at the beginning of each image. Furthermore,the module EXS comprises an image counter, for example a 40 ms counter,which is not shown on FIG. 2. The output of this image counterprogresses according to the counting ramp, crossing 0 at each imageperiod, that is every 40 ms in the case of the image counter cited inthe aforementioned example.

The image counter delivers a stair-step signal. The steps have a unitaryheight. The signal range value, that is to say the height correspondingto the difference in level between the highest step and the lowest stepis equal to 40 ms.F_(out), where F_(out) is the frequency of the videoclock Clk. The counter CPT successively delivers all of the integervalues from 0 to 40 ms.F_(out)−1.

The timing video clock is used to determine the rhythm of a counterCPT_PCR. The output of the counter CPT_PCR is a counting ramp, whoseperiod is m image periods. Every “m” image, the counter CPT_PCR isreset, that is to say that the counting ramp CSE_PCR is reset to 0.

“Counting ramp” designates a stair-step signal whose steps have aunitary height (or count increment ΔC). The signal range value, that isto say the height corresponding to the difference in level between thehighest step and the lowest step is equal to m.40 ms.F_(out). Thecounter CPT_PCR₁ delivers successively all of the integer values from 0to m.40 ms.F_(out)−1.

Next, a module LCH samples the counting ramp CSE_PCR every T_(ech)period to produce samples PCR_(e). These samples PCR_(e) are sent acrossthe network and reach the reception side through a network interface(block INTE).

FIG. 3 shows the reception side according to the prior art. Theinterface I_IPA recovers the PCR samples that have been sent on thenetwork. These samples PCR_(e) are received by a network interface(module INTR) with a delay linked to the transport between thetransmission device and the reception device: the module INTR producessamples PCR_(r). The samples PCR_(e), which are produced at regularT_(ech) intervals on the transmission side, arrive at irregularintervals on the reception side: this is largely due to the jitterintroduced during transport on the network. The samples PCR_(r) aretaken into account at regular T_(ech) intervals and hence, the majorityof the jitter introduced during packet transport is eliminated.

The imprecision between the transmission and reception sampling times isabsorbed by a phase-locked loop PLL₁ whose bandwidth is appropriated.The characteristics of the phase-locked loop PLL₁ guarantee areconstituted clock generation CLK_out₁ with a reduced jitter.

The phase-locked loop PLL₁ acts as a system receiving PCR_(r) samplesand delivering:

-   -   a reconstituted clock CLK_out₁,    -   a counting ramp CSR_PCR₁ and,    -   local samples PCR_loc₁.

When the loop PLL₁ operates in a steady state, the samples PCR_(r) arenoticeably equal to the samples PCR_loc₁.

The reconstituted clock CLK_out₁ determines the rhythm of a CPT imagecounter similar to the image counter on the transmission side, forexample a 40 ms counter. The image counter CPT is reset each time thecounting ramp CSR_PCR₁ crosses 0. Between two successiveinitialisations, the image counter CPT progresses freely and produces animage cue that supplies a local Genlock generator, GEG to produce areconstructed Genlock signal SG1, SG2 designed to synchronise thecameras CAM1, CAM2.

The reconstructed Genlock signal SG1, SG2 that is generated from thecounting ramp CSR_PCR₁ and the reconstituted clock CLK_out₁ is in phasewith the Genlock signal SG0 on the transmission side, to the nearestclock pulse.

FIG. 4 diagrammatically shows a PLL₁ phase-locked loop architecture usedin an I_IPA interface according to the prior art.

As shown in FIG. 4, the phase locking loop PLL₁ comprises:

-   -   a sample comparator CMP₁ that compares the samples PCR_(r) and        local samples delivering a comparison result of the samples, or        an error signal ERR,    -   a corrector COR_(E) receiving the signal ERR and delivering a        corrected error signal ERC,    -   a configurable oscillator VCO₁ receiving the corrected error        signal ERC and delivering a reconstituted clock CLK_out₁, the        clock CLK_out₁ has a frequency that depends on the signal ERC,    -   a counter CPT_PCR1 that produces a counting ramp CSRPCR1        according to a rate that is printed by the reconstituted clock        CLK_out₁,    -   a support system with the value LATCH₁ that generates local        samples PCR_loc₁ from the values of the counting ramp CSR_PCR₁        at the times T_(ech),

FIG. 5 illustrates a sample locking loop PLL₁ of a reception device PLL₁according to the invention. The loop PLL₁ comprises the means MES₁ fordetermining the incrementing step ΔC.

Hereafter, it is considered that a counting ramp having value rangevalue E, takes successively all the integer values between 0 and E−1.

A pulse from the reconstituted clock CLK_out₁ is identified uniquely byan index i. The pulse i+1 follows chronologically the pulse i.

The counter CPT_PCR₁ receives a count increment value ΔC and uses it toproduce the counting ramp values CSR_PCR₁. A counting ramp value withthe index i+1 is deduced from a counting ramp value with the index i bya difference whose value is the count increment ΔC.

Advantageously, the count increment values ΔC are integers and signed.

Advantageously, the count increment values ΔC are determined from thefrequency value F_(out) of the reconstituted clock CLK_out₁.

Advantageously, a count increment value ΔC has an absolute value that isa function of the frequency value F_(ou), of the reconstituted clockCLK_out₁.

Advantageously, a count increment ΔC has a sign that is a function ofthe frequency value F_(out) of the reconstituted clock CLK_out₁.

Advantageously, the count increment values ΔC are determined theamplitude of the difference values (ERR), referred as |ERR| on drawings,and sign of the difference values (ERR), referred as sgn(ERR) ondrawings.

Advantageously, a count increment ΔC has a sign that is a function ofthe sign of the difference values ERR.

Advantageously, a count increment ΔC has an absolute value that is afunction of the amplitude of the difference ERR.

The invention is described in the preceding text as an example. It isunderstood that those skilled in the art are capable of producingvariants of the invention without leaving the scope of the patent.

1. Reception device able to receive packets in a packet switchingnetwork comprising at least two stations, said device comprising: meansfor receiving packets containing samples, said samples coming from datasampled every period, where is from a time base synchronised on all thestations of said network, means for regenerating a counting ramp havinga count increment value and a range value PCR_Modulus, using aphase-locked loop receiving the samples and further delivering localsamples every T_(ech) period and a reconstituted clock with a frequencyvalue F_(out), means for initialising, at every zero-crossing of thecounting ramp, an image counter that is determined by the reconstitutedclock, means for generating image cues at every zero-crossing of saidcounter, and means for reconstituting a synchronization signal from saidimage cues, wherein it comprises, further, means for determining thecount increments values.
 2. Reception device according to claim 1,wherein the count increment values are integers and signed.
 3. Receptiondevice according to claim 2, wherein the count increment values aredetermined from the frequency value F_(out) of the reconstituted clock.4. Reception device according to claim 3, wherein a count incrementvalue has an absolute value that is a function of the frequency valueF_(out) of the reconstituted clock.
 5. Reception device according toclaim 3, wherein a count increment value has a sign that is a functionof the frequency value Fort of the reconstituted clock.
 6. Receptiondevice according to claim 2, difference values between local samples andsamples being calculated, wherein the count increment values aredetermined from the amplitude of the difference values and sign of thedifference values.
 7. Reception device according claim 6, wherein thecount increment has a sign that is a function of the sign of differencevalues.
 8. Reception device according claim 6, wherein a count incrementhas an absolute value that is a function of amplitude of the differencevalues.